Celeron M

• Banias-512 0.13 µm process technology
• Introduced March 2003
• 64 KB L1 cache
• 512 KB L2 cache (integrated)
• SSE2 SIMD instructions
• No SpeedStep technology, is not part of the 'Centrino' package
• Family 6 model 9
• Variants
• 310 - 1.20 GHz
• 320 - 1.30 GHz
• 330 - 1.40 GHz
• 340 - 1.50 GHz
• Dothan-1024 90 nm process technology
• 64 KB L1 cache
• 1 MB L2 cache (integrated)
• SSE2 SIMD instructions
• No SpeedStep technology, is not part of the 'Centrino' package
• Variants
• 350 - 1.30 GHz
• 350J - 1.30 GHz, with Execute Disable bit
• 360 - 1.40 GHz
• 360J - 1.40 GHz, with Execute Disable bit
• 370 - 1.50 GHz, with Execute Disable bit
• Family 6, Model 13, Stepping 8
• 380 - 1.60 GHz, with Execute Disable bit
• 390 - 1.70 GHz, with Execute Disable bit
• Yonah-1024 65 nm process technology
• 64 KB L1 cache
• 1 MB L2 cache (integrated)
• SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
• No SpeedStep technology, is not part of the 'Centrino' package
• Variants
• 410 - 1.46 GHz
• 420 - 1.60 GHz,
• 423 - 1.06 GHz (ultra low voltage)
• 430 - 1.73 GHz
• 440 - 1.86 GHz
• 443 - 1.20 GHz (ultra low voltage)
• 450 - 2.00 GHz