32-bit processors: the 80386 range

80386DX

• Introduced October 17, 1985
• Clock speeds:
• 16 MHz with 5 to 6 MIPS
• 20 MHz with 6 to 7 MIPS, introduced 16 February 1987
• 25 MHz with 8.5 MIPS, introduced 4 April 1988
• 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989
• Bus Width 32 bits
• Number of Transistors 275,000 at 1 µm
• Addressable memory 4 GB (4 GB)
• Virtual memory 64 TB (64 TiB)
• First x86 chip to handle 32-bit data sets
• Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
• Used in Desktop computing

80386SX

• Introduced June 16, 1988
• Clock speeds:
• 16 MHz with 2.5 MIPS
• 20 MHz with 2.5 MIPS, 25 MHz with 2.7 MIPS, introduced 25 January 1989
• 33 MHz with 2.9 MIPS, introduced 26 October 1992
• Internal architecture 32 bits
• External data bus width 16 bits
• External address bus width 24 bits
• Number of Transistors 275,000 at 1 µm
• Addressable memory 16 MB
• Virtual memory 32 GB
• Narrower buses enable low-cost 32-bit processing
• Used in entry-level desktop and portable computing
• No Math Co-Processor

80376

• Introduced January 16, 1989; Discontinued June 15, 2001
• Variant of 386 intended for embedded systems
• No "real mode", starts up directly in "protected mode"
• Replaced by much more successful 80386EX from 1994

80386SL

• Introduced October 15, 1990
• Clock speeds:
• 20 MHz with 4.21 MIPS
• 25 MHz with 5.3 MIPS, introduced 30 September ,1991
• Internal architecture 32 bits
• External bus width 16 bits
• Number of Transistors 855,000 at 1 µm
• Addressable memory 4 GB
• Virtual memory 1 TB
• First chip specifically made for portable computers because of low power consumption of chip
• Highly integrated, includes cache, bus, and memory controller

80386EX

• Introduced August 1994
• Variant of 80386SX intended for embedded systems
• Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
• On-chip peripherals:
• Clock and power mgmt
• Timers/counters
• Watchdog timer
• Serial I/O units (sync and async) and parallel I/O
• DMA
• RAM refresh
• JTAG test logic
• Significantly more successful than the 80376
• Used aboard several orbiting satellites and microsatellites
• Used in NASA's FlightLinux project

[9] 32-bit processors: the 80486 range

80486DX

• Introduced April 10, 1989
• Clock speeds:
• 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
• 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced 7 May 1990
• 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced 24 June 1991
• Bus Width 32 bits
• Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
• Addressable memory 4 GB
• Virtual memory 1 TB
• Level 1 cache of 8 KB on chip
• Math coprocessor on chip
• 50X performance of the 8088
• Used in Desktop computing and servers
• Family 4 model 3

80486SX

• Introduced April 22, 1991
• Clock speeds:
• 16 MHz with 13 MIPS
• 20 MHz with 16.5 MIPS, introduced 16 September 1991
• 25 MHz with 20 MIPS (12 SPECint92), introduced 16 September 1991
• 33 MHz with 27 MIPS (15.86 SPECint92), introduced 21 September 1992
• Bus Width 32 bits
• Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
• Addressable memory 4 GB
• Virtual memory 1 TB
• Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathco in the chip and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 turned on)
• Used in low-cost entry to 486 CPU desktop computing
• Upgradable with the Intel OverDrive processor
• Family 4 model 2

80486DX2

• Introduced March 3, 1992
• Clock speeds:
• 40 MHz
• 50 MHz
• 66 MHz
• 100 MHz (This was only made a short time due to high failure rates.)

80486SL

• Introduced November 9, 1992
• Clock speeds:
• 20 MHz with 15.4MIPS
• 25 MHz with 19 MIPS
• 33 MHz with 25 MIPS
• Bus Width 32 bits
• Number of Transistors 1.4 million at 0.8 µm
• Addressable memory 4 GB
• Virtual memory 1 TB
• Used in notebook computers
• Family 4 model 3

80486DX4

• Introduced March 7, 1994
• Clock speeds:
• 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
• 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
• Number of Transistors 1.6 million at 0.6 µm
• Bus width 32 bits
• Addressable memory 4 GB
• Virtual memory 64 TB
• Pin count 168 PGA Package, 208 sq ftP Package
• Die size 345 mm²
• Used in high performance entry-level desktops and value notebooks
• Family 4 model 8